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description the CXP7500P10/7500p11 is a cmos 8-bit single chip microcomputer integrating on a single chip an a/d converter, serial interface, timer/counter, time-base timer, on-screen display function, i 2 c bus interface, pwm output, remote control reception circuit, hsync counter, watchdog timer, 32khz timer/counter besides the basic configurations of 8-bit cpu, rom, ram, i/o ports. the CXP7500P10/7500p11 also provides a sleep function that enables to lower the power consumption. CXP7500P10/7500p11 is the prom-incorporated version of the cxp750096/750010/750097/750011 with built-in mask rom. this provides the additional feature of being able to write directly into the program. thus, it is most suitable for evaluation use during system development and for small-quantity production. features a wide instruction set (213 instructions) which covers various types of data ?16-bit operation/multiplication and division/ boolean bit operation instructions minimum instruction cycle 167ns at 24mhz operation 122s at 32khz operation incorporated rom 120k bytes incorporated ram 2496 bytes (excludes vram for on-screen display) peripheral functions ?a/d converter 8-bit 6-channel successive approximation method (conversion time of 3.25s at 16mhz) ?serial interface 8-bit clock sync type (msb/lsb first selectable), 1 channel ?timer 8-bit timer 8-bit timer/counter 19-bit time-base timer 32khz timer/counter ?on-screen display (osd) function 24 32 dots, 512 character types, 15 character colors, 2 lines 32 characters, frame background 8 colors/half blanking, background on full screen 15 colors/half blanking edging/shadowing/rounding for every line, background with shadow for every character, double scanning, sprite osd 24 32 dots, 1 screen, 8 colors for every dot ?i 2 c bus interface ?pwm output 8 bits, 8 channels 14 bits, 1 channel ?remote control reception circuit 8-bit pulse measurement counter, 6-stage fifo ?hsync counter 2 channels ?watchdog timer interruption 13 factors, 13 vectors, multi-interruption possible standby mode sleep package 64-pin plastic sdip/qfp, 52-pin plastic sdip piggy/evaluation chip cxp750000 64-pin ceramic pqfp/psdip (supports custom font) perchase of sony's i 2 c components conveys a licence under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specifications as defined by philips. CXP7500P10/7500p11 cmos 8-bit single chip microcomputer ?1 e99104-ps sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. structure silicon gate cmos ic 64 pin sdip (plastic) 64 pin qfp (plastic) 52 pin sdip (plastic)
? 2 CXP7500P10/7500p11 a / d c o n v e r t e r f i f o r e m o c o n s e r i a l i n t e r f a c e u n i t 8 - b i t t i m e r 1 8 - b i t t i m e r / c o u n t e r 0 o n s c r e e n d i s p l a y h s y n c c o u n t e r 0 h s y n c c o u n t e r 1 i 2 c b u s i n t e r f a c e u n i t 8 b i t s p w m 8 c h ( 6 c h ) 1 4 b i t s p w m 1 c h p r e s c a l e r / t i m e - b a s e t i m e r w a t c h d o g t i m e r 3 2 k h z t i m e r / c o u n t e r r o m 1 2 0 k b y t e s r a m 2 4 9 6 b y t e s c l o c k g e n e r a t o r / s y s t e m c o n t r o l i n t e r r u p t c o n t r o l l e r p o r t a p o r t b p o r t c p o r t d p o r t e p o r t f p o r t g p g 3 t o p g 6 * , p g 7 p w m 5 p f 0 t o p f 7 8 p e 4 t o p e 6 3 p e 2 , p e 3 2 p e 0 , p e 1 2 p d 0 t o p d 7 8 p c 6 , p c 7 * 2 p c 0 t o p c 5 * 6 p b 0 t o p b 7 8 p a 0 t o p a 7 8 p w m 0 t o p w m 7 a d j s c l 1 s c l 0 s d a 1 s d a 0 h s 1 h s 0 v s y n c h s y n c y m y s i b g r e x l c x l c t o e c s c k s o s i r m c a n 0 t o a n 5 6 2 2 2 i n t 0 i n t 1 i n t 2 t e x t x e x t a l x t a l v d d v s s r s t 8 ( 6 ) s p c 7 0 0 a i i c p u c o r e v p p block diagram * not incorrporated for 52-pin package. parentheses indicate configurations for 52-pin package.
? 3 CXP7500P10/7500p11 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 3 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 6 3 6 4 6 1 6 2 3 1 3 2 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 1 v s s v d d v p p e x l c x l c p e 4 / y m p e 5 / y s p e 6 / i b g r p b 0 p b 1 p b 2 p g 3 p g 4 p c 4 p c 5 p c 6 / p w m 6 p c 7 / p w m 7 p f 0 / p w m 0 p f 1 / p w m 1 p f 2 / p w m 2 p f 3 / p w m 3 p f 4 / s c l 0 p f 5 / s c l 1 / p w m 4 p f 6 / s d a 0 p f 7 / s d a 1 / p w m 5 p e 0 / t o / a d j p e 1 / p w m p e 2 / t e x / i n t 0 p e 3 / t x p d 4 / h s 0 p c 3 p c 2 p c 1 p c 0 p d 7 / e c p d 6 / r m c p d 5 / h s 1 p d 3 / s i p d 2 / s o p d 1 / s c k p d 0 / i n t 2 p a 7 / h s y n c p a 6 / v s y n c r s t v s s p a 0 / a n 0 x t a l e x t a l p a 5 / a n 5 p a 4 / a n 4 p a 3 / a n 3 p a 2 / a n 2 p a 1 / a n 1 p b 7 p b 6 p b 5 p b 4 p b 3 p g 7 / i n t 1 p g 6 p g 5 pin assignment (top view) 64-pin sdip note) 1. vpp (pin 46) is left open. 2. vss (pins 16 and 48) are both connected to gnd.
? 4 CXP7500P10/7500p11 v s s v d d v p p e x l c x l c p e 4 / y m p e 5 / y s p e 6 / i b g p e 1 / p w m p e 2 / t e x / i n t 0 p e 3 / t x p f 3 / p w m 3 p f 4 / s c l 0 p f 5 / s c l 1 / p w m 4 p f 6 / s d a 0 p f 7 / s d a 1 / p w m 5 p e 0 / t o / a d j 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 3 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 5 1 p f 2 / p w m 2 p f 1 / p w m 1 p f 0 / p w m 0 p c 7 / p w m 7 p c 6 / p w m 6 p c 5 p c 4 p c 3 p c 2 p c 1 p c 0 p d 7 / e c p d 6 / r m c 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 6 3 6 4 6 1 6 2 r p b 0 p b 1 p b 2 p g 3 p g 4 p g 5 p g 6 p g 7 / i n t 1 p b 3 p b 4 p b 5 p b 6 3 1 3 2 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 p d 4 / h s 0 p d 5 / h s 1 p d 3 / s i p d 2 / s o p d 1 / s c k p d 0 / i n t 2 p a 7 / h s y n c p a 6 / v s y n c r s t v s s p a 0 / a n 0 x t a l e x t a l p a 5 / a n 5 p a 4 / a n 4 p a 3 / a n 3 p a 2 / a n 2 p a 1 / a n 1 p b 7 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 1 pin assignment (top view) 64-pin qfp note) 1. vpp (pin 40) is left open. 2. vss (pins 10 and 42) are both connected to gnd.
? 5 CXP7500P10/7500p11 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 3 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 5 1 5 2 3 1 3 2 2 7 2 8 2 9 3 0 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 1 p d 4 / h s 0 p d 7 / e c p d 6 / r m c p d 5 / h s 1 p d 3 / s i p d 2 / s o p d 1 / s c k p d 0 / i n t 2 p a 7 / h s y n c p a 6 / v s y n c r s t v s s p a 0 / a n 0 x t a l e x t a l p a 5 / a n 5 p a 4 / a n 4 p a 3 / a n 3 p a 2 / a n 2 p a 1 / a n 1 p b 7 p b 6 p b 5 p b 4 p b 3 p g 7 / i n t 1 v s s v d d v p p e x l c x l c p e 4 / y m p e 5 / y s p e 6 / i b g r p b 0 p b 1 p b 2 p f 0 / p w m 0 p f 1 / p w m 1 p f 2 / p w m 2 p f 3 / p w m 3 p f 4 / s c l 0 p f 5 / s c l 1 / p w m 4 p f 6 / s d a 0 p f 7 / s d a 1 / p w m 5 p e 0 / t o / a d j p e 1 / p w m p e 2 / t e x / i n t 0 p e 3 / t x pin assignment (top view) 52-pin sdip note) 1. vpp (pin 38) is left open. 2. vss (pins 12 and 40) are both connected to gnd.
? 6 CXP7500P10/7500p11 (port a) 8-bit i/o port. i/o can be set in a unit of single bits. (8 pins) (port b) 8-bit i/o port. i/o can be set in a unit of single bits. (8 pins) (port c) lower 6 bits are i/o ports; i/o can be set in a unit of single bits. upper 2 bits are output port and large current (12ma) n-channel open drain output. upper 2 bits are medium drive voltage (12v); lower 6 bits are 5v drive. (8 pins) (port d) 8-bit i/o port. i/o can be set in a unit of single bits. can drive 12ma sink current. (8 pins) (port e) bits 0 and 1 are i/o port; i/o can be set in a unit of single bits. bits 2 and 3 are input port. bits 4, 5 and 6 are output port. (7 pins) pin description symbol pa0/an0 to pa5/an5 pa6/vsync pa7/hsync pb0 to pb7 pc0 to pc5 * pc6/pwm6 * to pc7/pwm7 * pd0/int2 pd1/sck pd2/so pd3/si pd4/hs0 pd5/hs1 pd6/rmc pd7/ec pe0/to/adj pe1/pwm pe2/tex/int0 pe3/tx pe4/ym pe5/ys pe6/i b g r i/o/ analog input i/o/input i/o/input i/o i/o output/output i/o/input i/o/i/o i/o/output i/o/input i/o/input i/o/input i/o/input i/o/input i/o/output/ output i/o/output input/input/ input input output/output output/output output/output output output output i/o description analog inputs to a/d converter. (6 pins) osd display vertical sync signal input. osd display horizontal sync signal input. 8-bit pwm output. (2 pins) external interruption request input. active at the falling edge. serial clock i/o. serial data output. serial data input. hsync counter (ch0) input. hsync counter (ch1) input. remote control reception circuit input. external event input for timer/counter. rectangular wave output for 8-bit timer/counter. 14-bit pwm output. connects a crystal for 32khz timer/counter clock oscillation. when used as an event counter, input to tex pin and leave tx pin open. tex oscillation frequency dividing output. external interruption request input. active at the falling edge. osd display 6-bit output. (6 pins) * not incorporated for 52-pin package.
? 7 CXP7500P10/7500p11 (port f) 8-bit output port and large current (12ma) n-channel open drain output. lower 4 bits are medium drive voltage (12v); upper 4 bits are 5v drive. (8 pins) (port g) 5-bit i/o port. i/o can be set in a unit of single bits. (5 pins) connects a crystal for system clock oscillation. when a clock is supplied externally, input to extal pin and input a reversed phase clock to xtal pin. system reset; active at low level. osd display clock oscillation i/o. oscillation frequency is determined by the external l and c. positive power supply for incorporated prom writing. leave this pin open during normal operation. positive power supply. gnd. connect two vss pins to gnd. 8-bit pwm output. (4 pins) i 2 c bus interface transfer clock i/o. (2 pins) i 2 c bus interface transfer data i/o. (2 pins) symbol pf0/pwm0 to pf3/pwm3 pf4/scl0 pf5/scl1/ pwm4 pf6/sda0 pf7/sda1/ pwm5 pg3 to pg6 * pg7/int1 extal xtal rst exlc xlc vpp v dd vss output/output output/i/o output/i/o/ output output/i/o output/i/o/ output i/o i/o/input input input input i/o description 8-bit pwm output. 8-bit pwm output. external interruption request input. active at the falling edge. * not incorporated for 52-pin package.
? 8 CXP7500P10/7500p11 p o r t a d a t a p o r t a d i r e c t i o n i p r d ( p o r t a ) i n t e r n a l d a t a b u s 0 a f t e r a r e s e t p o r t a f u n c t i o n s e l e c t i o n 0 a f t e r a r e s e t a / d c o n v e r t e r i n p u t m u l t i p l e x e r i n p u t p r o t e c t i o n c i r c u i t p o r t a d a t a p o r t a d i r e c t i o n i p i n p u t p o l a r i t y r d ( p o r t a ) i n t e r n a l d a t a b u s h s y n c , v s y n c 0 a f t e r a r e s e t 0 a f t e r a r e s e t s c h m i t t i n p u t p o r t s b , c , g d a t a p o r t s b , c , g d i r e c t i o n i p r d ( p o r t s b , c , g ) i n t e r n a l d a t a b u s i n t 1 0 a f t e r a r e s e t p b 0 t o p b 2 s c h m i t t i n p u t o n l y f o r p g 7 input/output circuit formats for pins port a port a port b port c 6 pins 2 pins 19 pins hi-z hi-z hi-z pin after a reset circuit format pa6/vsync pa7/hsync pb0 to pb7 pc0 to pc5 * pg3 to pg6 * pg7/int1 pa0/an0 to pa5/an5 port g p o r t s c , f d a t a p o r t s c , f f u n c t i o n s e l e c t i o n 0 a f t e r a r e s e t 1 a f t e r a r e s e t p w m 0 t o p w m 3 p w m 6 , p w m 7 * 1 2 v d r i v e v o l t a g e l a r g e c u r r e n t 1 2 m a * r d ( p o r t s c , f ) i n t e r n a l d a t a b u s port c 6 pins pc6/pwm6 * pc7/pwm7 * pf0/pwm0 to pf3/pwm3 hi-z port f * not incorporated for 52-pin package.
? 9 CXP7500P10/7500p11 p o r t d d a t a p o r t d d i r e c t i o n i p r d ( p o r t d ) i n t e r n a l d a t a b u s i n t 2 , s i , h s 0 , h s 1 , r m c , e c 0 a f t e r a r e s e t s c h m i t t i n p u t * l a r g e c u r r e n t 1 2 m a * p o r t d d a t a p o r t d d i r e c t i o n i p r d ( p o r t d ) i n t e r n a l d a t a b u s 0 a f t e r a r e s e t s c h m i t t i n p u t o n l y f o r p d 1 s c k , s o s i o o u t p u t e n a b l e s c k o n l y * l a r g e c u r r e n t 1 2 m a * p o r t e d a t a 1 a f t e r a r e s e t t o a d j 1 6 k a d j 2 k * 1 * 1 0 1 0 0 1 0 1 1 m p x i n t e r n a l d a t a b u s p o r t e d i r e c t i o n 1 a f t e r a r e s e t 0 0 a f t e r a r e s e t i p 1 a f t e r a r e s e t * 2 * 1 a d j s i g n a l s a r e f r e q u e n c y d i v i d i n g o u t p u t s f o r 3 2 k h z o s c i l l a t i o n f r e q u e n c y a d j u s t m e n t . a d j 2 k p r o v i d e s u s a g e a s b u z z e r o u t p u t . * 2 p u l l - u p t r a n s i s t o r s a p p r o x . 1 5 0 k w r d ( p o r t e ) p o r t e f u n c t i o n s e l e c t i o n ( l o w e r ) p o r t e f u n c t i o n s e l e c t i o n ( u p p e r ) port d port d port e 6 pins 2 pins 1 pin hi-z hi-z high level h level at on resistance of pull-up transistor during a reset pin after a reset circuit format pd1/sck pd2/so pe0/to/adj pd0/int2 pd3/si pd4/hs0 pd5/hs1 pd6/rmc pd7/ec ( )
? 10 CXP7500P10/7500p11 i p i p r d ( p o r t e ) s c h m i t t i n p u t s c h m i t t i n p u t c l o c k i n p u t i n t r e n a l d a t a b u s i n t r e n a l d a t a b u s i n t 0 1 a f t e r a r e s e t p e 2 / t e x / i n t 0 p e 3 / t x r d ( p o r t e ) t e x o s c i l l a t i o n c i r c u i t c o n t r o l p o r t e d a t a p o r t e d i r e c t i o n i p r d ( p o r t e ) i n t e r n a l d a t a b u s 1 a f t e r a r e s e t p w m 1 a f t e r a r e s e t p o r t e f u n c t i o n s e l e c t i o n 0 a f t e r a r e s e t port e port e 1 pin 2 pins 3 pins pin after a reset circuit format pe2/tex/int0 pe3/tx high level oscillation stop port input hi-z pe1/pwm pe4/ym pe5/ys pe6/i p o r t e d a t a p o r t e f u n c t i o n s e l e c t i o n 1 a f t e r a r e s e t y m , y s , i o u t p u t p o l a r i t y 0 a f t e r a r e s e t w r i t i n g d a t a t o o u t p u t p o l a r i t y r e g i s t e r o r p o r t d a t a r e g i s t e r b r i n g s o u t p u t t o a c t i v a t e . r d ( p o r t e ) i n t e r n a l d a t a b u s port e
? 11 CXP7500P10/7500p11 4 pins 3 pins pin after a reset circuit format r g b hi-z hi-z i 2 c b u s e n a b l e p o r t f d a t a p o r t f f u n c t i o n s e l e c t i o n 0 a f t e r a r e s e t 1 a f t e r a r e s e t p w m 4 , p w m 5 s c l , s d a s c l , s d a ( i 2 c b u s c i r c u i t ) i p s c h m i t t i n p u t * l a r g e c u r r e n t 1 2 m a t o i n t e r n a l i 2 c p i n s ( s c l 1 f o r s c l 0 ) b u s s w * r d ( p o r t f ) i n t e r n a l d a t a b u s r , g , b o u t p u t p o l a r i t y 0 a f t e r a r e s e t w r i t i n g d a t a t o o u t p u t p o l a r i t y r e g i s t e r b r i n g s o u t p u t t o a c t i v a t e . port f pf4/scl0 pf5/scl1/pwm4 pf6/sda0 pf7/sda1/pwm5 e x l c x l c i p o s c i l l a t i o n c o n t r o l i p o s d d i s p l a y c l o c k i p e x t a l x t a l d i a g r a m s h o w s t h e c i r c u i t c o m p o s i t i o n d u r i n g o s c i l l a t i o n . f e e d b a c k r e s i s t o r i s r e m o v e d a n d x t a l i s d r i v e n a t " h " l e v e l d u r i n g s t o p . ( t h i s d e v i c e d o e s n o t e n t e r t h e s t o p m o d e . ) a a a a s c h m i t t i n p u t p u l l - u p r e s i s t o r 2 pins exlc xlc 2 pins extal xtal 1 pin rst oscillation stop oscillation low level (during a reset)
? 12 CXP7500P10/7500p11 * 1 v in and v out should not exceed v dd + 0.3v. * 2 the large current drive transistor is port c (pc6, pc7), port d (pd) and port f (pf). note) usage exceeding absolute maximum ratings may permanently impair the lsi. normal operation should be conducted under the recommended operating conditions. exceeding those conditions may adversely affect the reliability of the lsi. v dd vpp v in v out v outp i oh i oh i ol i olc i ol topr tstg p d ?.3 to +7.0 ?.3 to +13.0 ?.3 to +7.0 * 1 ?.3 to +7.0 * 1 ?.3 to +15.0 ? ?0 15 20 130 ?0 to +75 ?5 to +150 1000 600 875 v v v v v ma ma ma ma ma c c mw mw mw incorporated prom total of all output pins pins excluding large current output (value per pin) large current output pins * 2 (value per pin) total of all output pins sdip-64p-01 qfp-64p-l01 sdip-52p-01 item symbol ratings unit remarks absolute maximum ratings (vss = 0v reference) supply voltage input voltage output voltage medium drive output voltage high level output current high level total output current low level output current low level total output current operating temperature storage temperature allowable power dissipation
? 13 CXP7500P10/7500p11 supply voltage high level input voltage low level input voltage operating temperature 5.5 5.5 5.5 v dd v dd v dd + 0.3 0.3v dd 0.2v dd 0.4 +75 v v v v v v v v v v c item symbol min. max. unit remarks 4.5 3.5 2.7 0.7v dd 0.8v dd v dd ?0.4 0 0 ?.3 ?0 v ih v ihs v ihex v il v ils v ilex topr guaranteed operation range for 1/2 and 1/4 frequency dividing modes guaranteed operation range for 1/16 frequency dividing mode or sleep guaranteed operation range for tex mode guaranteed data hold range for stop * 5 * 1 * 2 extal pin * 3 , tex pin * 4 * 1 * 2 extal pin * 3 , tex pin * 4 v dd * 1 pa0 to pa5, pb3 to pb7, pc0 to pc5, pd2, pe0, pe1, pe3, pg3 to pg6, scl0, scl1, sda0, sda1 pins * 2 vsync, hsync, int2, sck, si, hs0, hs1, rmc, ec, int0, int1, rst, pb0 to pb2 pins * 3 specifies only during external clock input. * 4 specifies only during external event count input. * 5 this device does not enter the stop mode. recommended operating conditions (vss = 0v reference)
? 14 CXP7500P10/7500p11 v dd = 4.5v, i oh = ?.5ma v dd = 4.5v, i oh = ?.2ma v dd = 4.5v, i ol = 1.8ma v dd = 4.5v, i ol = 3.6ma v dd = 4.5v, i ol = 3.0ma v dd = 4.5v, i ol = 4.0ma v dd = 5.5v, v ih = 5.5v v dd = 5.5v, v il = 0.4v v dd = 5.5v, v ih = 5.5v v dd = 4.5v, i ol = 12.0ma high level output voltage low level output voltage input current i/o leakage current open drain i/o leakage current (in n-ch tr off state) supply current * 2 4.0 3.5 27 40 2.2 17 a ma a a 50 10 120 42 40 63 95 3.9 45 ma a a 0.4 0.6 1.5 0.4 0.6 40 ?0 10 ?0 ?00 10 v v v v v a a a a a a 0.5 ?.5 0.1 ?.1 ?.5 v v pa, pb, pc0 to pc5, pd, pe0 to pe1, pe4 to pe6, pg, r, g, b pa to pd, pe0 to pe1, pe4 to pe6, pf0 to pf3, pg, r, g, b pc6, pc7, pd, pf pf4 to pf7 (scl0, scl1, sda0, sda1) extal rst * 1 pa , pb, pc0 to pc5,pd, pe , pg, r, g, b, rst * 1 pc6, pc7, pf0 to pf3 pf4 to pf7 scl0: scl1 sda0: sda1 v dd = 5.5v, v il = 0.4v v dd = 5.5v, v i = 0, 5.5v v dd = 5.5v, v oh = 12.0v v dd = 5.5v, v oh = 5.5v v dd = 4.5v v scl0 = v scl1 = 2.25v v sda0 = v sda1 = 2.25v v dd v dd = 3.3v, 32khz crystal oscillation (c 1 = c 2 = 47pf) item symbol pins conditions min. typ. max. unit v oh v ol i iz i loh r bs i dd1 i dd2 i dds1 i dds2 i dds3 i ihe i ile i iht i ilt i ilr electrical characteristics dc characteristics (ta = ?0 to +75 c, vss = 0v reference) 1/2 frequency dividing mode tex v dd = 5.5v, 16mhz crystal oscillation (c 1 = c 2 = 15pf) v dd = 5.5v, 24mhz crystal oscillation v dd = 3.3v, 32khz crystal oscillation (c 1 = c 2 = 47pf) sleep mode v dd = 5.5v, 24mhz crystal oscillation (c 1 = c 2 = 15pf) stop mode * 3 v dd = 5.5v, termination of 24mhz and 32khz oscillation i 2 c bus switch connection impedance (in output tr off state)
? 15 CXP7500P10/7500p11 * 1 for rst pin, specifies the input current when pull-up resistance is selected, and specifies the leakage current when non-resistor is selected. * 2 when all output pins are left open. specifies only when the osd oscillation is stopped. * 3 this device does not enter the stop mode. input capacitance 10 20 pf pa, pb,pc0 to pc5, pd,pe0 to pe3, pf4 to pf7, pg, extal, exlc, rst clock 1mhz 0v other than the measured pins item symbol pins conditions min. typ. max. unit c in
? 16 CXP7500P10/7500p11 * 1 indicates three values according to the contents of the clock control register (clc: 000feh) upper 2 bits (cpu clock selection). t sys [ns] = 2000/fc (upper 2 bits = ?0?, 4000/fc (upper 2 bits = ?1?, 16000/fc (upper 2 bits = ?1? e x t a l t x h t x l t c f t c r 0 . 4 v v d d 0 . 4 v 1 / f c a a a a a a a a a a a a a a a a c r y s t a l o s c i l l a t i o n c e r a m i c o s c i l l a t i o n e x t a l x t a l e x t e r n a l c l o c k e x t a l x t a l 7 4 h c 0 4 c 1 c 2 a a a a a a a a 3 2 k h z c l o c k a p p l i e d c o n d i t i o n c r y s t a l o s c i l l a t i o n t e x t x c 1 c 2 t e x e c t e h t e l t e f t e r 0 . 2 v d d 0 . 8 v d d t t h t t l t t f t t r ac characteristics (1) clock timing system clock frequency system clock input pulse width system clock input rise and fall times event count input clock pulse width event count input clock rise and fall times system clock frequency event count input clock input pulse width event count input clock rise and fall times f c t xl , t xh t cr , t cf t eh , t el t er , t ef f c t tl , t th t tr , t tf xtal extal extal extal ec ec tex tx tex tex mhz ns ns ns ms khz s ms item symbol pins conditions min. unit fig. 1, fig.2 fig. 1, fig.2 external clock drive fig. 1, fig.2 external clock drive fig. 3 fig. 3 v dd = 2.7 to 5.5v fig. 2 (32khz clock applied conditions) fig. 3 fig. 3 8 17 4 t sys * 1 10 typ. 32.768 max 24 200 20 20 (ta = ?0 to +75 c, v dd = 4.5 to 5.5v, vss = 0v reference) fig.2. clock applied conditions fig. 1. clock timing fig. 3. event count clock timing
0 . 2 v d d 0 . 8 v d d t k l t k h s o t k c y t s i k t k s i 0 . 2 v d d 0 . 8 v d d t k s o 0 . 2 v d d 0 . 8 v d d o u t p u t d a t a i n p u t d a t a s i s c k ? 17 CXP7500P10/7500p11 (2) serial transfer (ta = ?0 to +75 c, v dd = 4.5 to 5.5v, vss = 0v reference) item sck cycle time t kcy sck input mode output mode sck input mode sck output mode sck input mode sck output mode sck input mode sck output mode sck input mode sck output mode 1000 8000/fc 400 4000/fc ?50 100 200 200 100 200 100 ns ns ns ns ns ns ns ns ns ns sck si si so t kh t kl t sik t ksi t kso sck high and low level width si input setup time (for sck - ) si hold time (for sck - ) sck ? so delay time symbol pins conditions min. max. unit note) the load of sck output mode and so output delay time is 50pf + 1ttl. fig. 4. serial transfer timing
? 18 CXP7500P10/7500p11 resolution linearity error zero transition voltage full-scale transition voltage conversion time sampling time analog input voltage v zt * 1 v ft * 2 t conv t samp v ian an0 to an5 ta = 25 c v dd = 5.0v vss = 0v ?0 4910 26/f adc * 3 6/f adc * 3 0 10 4970 8 3 70 5030 v dd bits lsb mv mv s s v item symbol pins conditions min. typ. max. unit (3) a/d converter (ta = ?0 to +75 c, v dd = 4.5 to 5.5v, vss = 0v reference) l i n e a r i t y e r r o r v z t v f t a n a l o g i n p u t f f h f e h 0 1 h 0 0 h d i g i t a l c o n v e r s i o n v a l u e fig. 5. definitions for a/d converter terms * 1 v zt : value at which the digital conversion value changes from 00h to 01h and vice versa. * 2 v ft : value at which the digital conversion value changes from feh to ffh and vice versa. * 3 f adc indicates the below values due to the contents of bit 6 (cks) of the a/d control register (adc: 000f6h): f adc = fc (cks = ??, fc/2 (cks = ??
? 19 CXP7500P10/7500p11 external interruption high, low level width reset input low level width int0 int1 int2 rst 1 32/fc s s item symbol pins conditions min. max. unit t ih t il t rsl (4) interruption, reset input (ta = ?0 to +75 c, v dd = 4.5 to 5.5v, vss = 0v reference) 0 . 2 v d d 0 . 8 v d d t i h t i l i n t 0 i n t 1 i n t 2 ( f a l l i n g e d g e ) fig. 6. interruption input timing t r s l 0 . 2 v d d r s t fig. 7. rst input timing
? 20 CXP7500P10/7500p11 (5) i 2 c bus timing (ta = ?0 to +75 c, v dd = 4.5 to 5.5v, vss = 0v reference) item scl clock frequency bus-free time before starting transfer hold time for starting transfer clock low level width clock high level width setup time for repeated transfers data hold time data setup time sda, scl rise time sda, scl fall time setup time for transfer completion f slc t buf t hd; sta t low t high t su; sta t hd; dat t su; dat t r t f t su; sto scl sda, scl sda, scl scl scl sda, scl sda, scl sda, scl sda, scl sda, scl sda, scl 0 4.7 4.0 4.7 4.0 4.7 0 * 1 250 4.7 100 1 300 khz s s s s s s ns s ns s symbol pins conditions min. max. unit * 1 the data hold time should be 300ns or more because the scl rise time (300ns max.) is not included in it. fig. 8. i 2 c bus transfer timing p s t t s u ; s t o t s u ; s t a t h d ; s t a t s u ; d a t t h i g h t h d ; d a t t f t r t l o w t h d ; s t a s p t b u f s d a s c l fig. 9. i 2 c bus device recommended circuit i 2 c b u s d e v i c e i 2 c b u s d e v i c e r s r s r s r s r p r p s d a 0 ( o r s d a 1 ) s c l 0 ( o r s c l 1 ) a pull-up resistor (rp) must be connected to sda0 (or sda1) and scl0 (or scl1). the sda0 (or sda1) and scl0 (or scl1) series resistance (rs = 300 or less) can be used to reduce the spike noise caused by crt flashover.
l c 2 c 1 e x l c x l c r * 3 ? 21 CXP7500P10/7500p11 (6) osd timing (ta = ?0 to +75 c, v dd = 4.5 to 5.5v, vss = 0v reference) item osd clock frequency hsync pulse width vsync pulse width hsync afterwrite rise and fall times vsync beforewrite rise and fall times f osc * 1 t hwd t vwd t hcg t vcg exlc xlc hsync vsync hsync vsync fig. 11 fig. 10 fig. 10 fig. 10 fig. 10 4 30/fc 1 40.8 200 1.0 mhz s h * 2 ns s symbol pins conditions unit min. max. fig. 10. osd timing 0 . 8 v d d 0 . 2 v d d t h c g t h w d h s y n c f o r o s d i / o p o l a r i t y r e g i s t e r ( o p o l : 0 0 1 f e h ) b i t 7 a t 0 0 . 8 v d d 0 . 2 v d d t v c g v s y n c f o r o s d i / o p o l a r i t y r e g i s t e r ( o p o l : 0 0 1 f e h ) b i t 6 a t 0 t v w d fig. 11. lc oscillation circuit connection * 3 the series resistor for xlc (r = 1k or less) can reduce the frequency of occurrence of the undesired radiation. * 1 the maximum value of fosc is specified with the following equation. fosc [max] fc 1.7 * 2 h indicates 1hsync period.
? 22 CXP7500P10/7500p11 appendix c 2 r d a a a a a a a a a a a a e x t a l x t a l c 1 ( i ) m a i n c l o c k a a a a a a a a a a a a a a a t e x t x c 1 c 2 r d ( i i i ) s u b c l o c k r d a a a a a a a a a a a a e x t a l x t a l c 1 c 2 ( i i ) m a i n c l o c k a a a a * models with an astarisk ( * ) have the built-in ground capacitance (c 1 , c 2 ). * 1 the series resistor for xtal (rd = 500 or less) can reduce the effect of the noise caused by the electrostatic discharge. manufacturer river eletec corporation murata mfg co., ltd. csa10.0mtz csa12.0mtz csa16.00mxz040 csa24.00mxz040 cst10.0mtw * cst12.0mtw * cst16.00mxw0c1 * kinseki ltd. seiko instruments inc. model hc-49/u03 hc-49/u (-s) p3 fc (mhz) 10.0 12.0 16.0 24.0 10.0 12.0 16.0 8.0 12.0 16.0 8.0 12.0 16.0 24.0 30 5 open 30 5 18 12 10 10 5 open 3 33 18 30 5 open 30 5 18 12 10 10 5 open 3 30 18 0 * 1 33 0 * 1 0 * 1 120k 32.768khz (iii) vtc-200 sp-t 330k 32.768khz (iii) c 1 (pf) c 2 (pf) rd ( ) circuit example remarks (i) (i) (ii) cl = 12.5pf fig. 12. recommended oscillation circuit mask option table item package rom capacitance reset pin pull-up resistor 64-pin plastic sdip/qfp 52-pin plastic sdip 96k/120k byte existent/non-existent 64-pin plastic sdip/qfp prom 120k byte existent 52-pin plastic sdip prom 120k byte existent mask rom CXP7500P10-1- cxp7500p11-2-
? 23 CXP7500P10/7500p11 fig. 13. characteristic curves 1 0 0 1 0 p a r a m e t e r c u r v e f o r o s d o s c i l l a t o r l v s . c ( a n a l y t i c a l l y c a l c u l a t e d v a l u e ) 1 0 . 1 0 . 0 1 l i n d u c t a n c e [ h ] c 1 , c 2 c a p a c i t a n c e [ p f ] 2 0 m h z 2 4 m h z 3 2 m h z 5 0 1 0 0 9 0 8 0 7 0 6 0 4 0 3 0 2 0 1 0 0 2 8 m h z 1 6 m h z 3 6 m h z 4 0 m h z 1 0 1 0 . 1 0 . 0 1 1 0 0 2 3 4 5 6 7 ( t a = 2 5 c , f c = 2 4 m h z , t y p i c a l ) v d d s u p p l y v o l t a g e [ v ] i d d s u p p l y c u r r e n t [ m a ] 1 / 4 d i v i d i n g m o d e 1 / 2 d i v i d i n g m o d e 3 2 k h z o p e r a t i o n m o d e 3 2 k h z s l e e p m o d e i d d v s . v d d 0 5 1 0 1 5 2 0 0 5 1 0 1 5 2 0 2 5 i d d v s . f c ( v d d = 5 . 0 v , t a = 2 5 c , t y p i c a l ) i d d s u p p l y c u r r e n t [ m a ] s l e e p m o d e 1 / 1 6 d i v i d i n g m o d e 1 / 4 d i v i d i n g m o d e 1 / 2 d i v i d i n g m o d e f c f r e q u e n c y [ m h z ] 2 5 3 0 3 0 3 5 4 0 1 0 1 0 . 1 0 . 0 1 1 0 0 2 3 4 5 6 7 ( t a = 2 5 c , f c = 1 6 m h z , t y p i c a l ) v d d s u p p l y v o l t a g e [ v ] i d d s u p p l y c u r r e n t [ m a ] s l e e p m o d e 1 / 4 d i v i d i n g m o d e 1 / 2 d i v i d i n g m o d e i d d v s . v d d 3 2 k h z s l e e p m o d e 3 2 k h z o p e r a t i o n m o d e 1 / 1 6 d i v i d i n g m o d e 1 / 1 6 d i v i d i n g m o d e s l e e p m o d e
? 24 CXP7500P10/7500p11 package outline unit: mm p a c k a g e s t r u c t u r e p a c k a g e m a t e r i a l l e a d t r e a t m e n t l e a d m a t e r i a l p a c k a g e m a s s s o n y c o d e e i a j c o d e j e d e c c o d e s d i p - 6 4 p - 0 1 4 2 a l l o y s o l d e r p l a t i n g e p o x y r e s i n 6 4 p i n s d i p ( p l a s t i c ) s d i p 0 6 4 - p - 0 7 5 0 5 7 . 6 0 . 1 + 0 . 4 6 4 3 3 1 3 2 1 . 7 7 8 1 9 . 0 5 1 7 . 1 0 . 1 + 0 . 3 0 t o 1 5 0 . 2 5 0 . 0 5 + 0 . 1 0 . 5 m i n 4 . 7 5 0 . 1 + 0 . 4 3 . 0 m i n 0 . 5 0 . 1 0 . 9 0 . 1 5 8 . 6 g s o n y c o d e e i a j c o d e j e d e c c o d e 2 3 . 9 0 . 4 2 0 . 0 0 . 1 0 . 4 0 . 1 + 0 . 1 5 1 4 . 0 0 . 1 1 1 9 2 0 3 2 3 3 5 1 5 2 6 4 0 . 1 5 0 . 0 5 + 0 . 1 2 . 7 5 0 . 1 5 1 6 . 3 0 . 1 0 . 0 5 + 0 . 2 0 . 8 0 . 2 m 0 . 2 0 . 1 5 + 0 . 4 1 7 . 9 0 . 4 + 0 . 4 + 0 . 3 5 6 4 p i n q f p ( p l a s t i c ) q f p - 6 4 p - l 0 1 q f p 0 6 4 - p - 1 4 2 0 p a c k a g e m a t e r i a l l e a d t r e a t m e n t l e a d m a t e r i a l p a c k a g e m a s s e p o x y r e s i n s o l d e r / p a l l a d i u m 4 2 / c o p p e r a l l o y p a c k a g e s t r u c t u r e p l a t i n g 1 . 5 g 1 . 0 0 t o 1 0
? 25 CXP7500P10/7500p11 p a c k a g e s t r u c t u r e p a c k a g e m a t e r i a l l e a d t r e a t m e n t l e a d m a t e r i a l p a c k a g e m a s s e p o x y r e s i n c o p p e r a l l o y 4 7 . 0 0 . 1 + 0 . 4 1 . 7 7 8 1 5 . 2 4 1 3 . 5 0 . 1 + 0 . 3 0 t o 1 5 0 . 2 5 0 . 0 5 + 0 . 1 0 . 5 0 . 1 0 . 9 0 . 0 5 + 0 . 1 2 . 8 m i n 0 . 5 1 m i n 5 . 0 m i n s d i p - 5 2 p - 0 1 s d i p 0 5 2 - p - 0 6 0 0 5 2 p i n s d i p ( p l a s t i c ) 5 2 1 2 6 2 7 s o n y c o d e e i a j c o d e j e d e c c o d e p l a t i n g s o l d e r / p a l l a d i u m 5 . 6 g

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